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TDA7437N
DIGITALLY CONTROLLED AUDIO PROCESSOR
s
INPUT MULTIPLEXER - FOUR STEREO, ONE MONO INPUT, AND ONE DIFFERENTIAL INPUT - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES
s
FULLY PROGRAMMABLE LOUDNESS FUNCTION VOLUME CONTROL IN 1dB STEPS INCLUDING GAIN UP TO 16dB ZERO CROSSING MUTE, SOFT MUTE AND DIRECT MUTE BASS AND TREBLE CONTROL FOUR SPEAKER ATTENUATORS- FOUR INDEPENDENT SPEAKERS CONTROL IN 1dB STEPS FOR BALANCE AND FADER FACILITIES PAUSE DETECTOR PROGRAMMABLE THRESHOLD ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2C BUS
TQFP44 ORDERING NUMBER: TDA7437N
s
s
DESCRIPTION The audioprocessor TDA7437N is an upgrade of the TDA731X audioprocessor family. Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained. Several new features like softmute, and zero-crossing mute are implemented.The soft Mute function can be activated in two ways: 1 Via serial bus (Mute byte, bit D0) 2 Directly on pin 28 through an I/O line of the microcontroller Very low DC stepping is obtained by use of a BICMOS technology.
s s
s
s
PIN DESCRIPTION (Top view)
OUT_LF 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 LOUD_L DIFFGND_L DIFF_L STEREO4_L STEREO1_L STEREO2_L STEREO3_L CSM IN_L MUXOUT_L MID_RI TREB-L PAUSE DGND AGND DVDD ADDR AVDD CREF SDA SCL
44 43 42 41 40 39 38 37 36 35 34 TREB_R IN_R MUXOUT_R LOUD_R DIFFGND_R DIFF_R STEREO4_R STEREO1_R STEREO2_R STEREO3_R MONO 1 2 3 4 5 6 7 8 9 10 11 OUT_RF OUT_LR MID_LI MID_LO OUT_RR SMEXT BASS_RO BASS_RI BASS_LO BASS_LI MID_RO
D96AU435B
October 2003
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ABSOLUTE MAXIMUM RATINGS
Symbol AVDD, DVDD Operating Supply Voltage Tamb Tstg Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -40 to 85 -55 to 150 Unit V C C
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction to pins Max. Value 150 Unit C/W
QUICK REFERENCE DATA
Symbol AVDD, DVDD VCL THD S/N SC Parameter Supply Voltage (AVDD and DVDD must be at the same potential) Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Channel Separation f = 1KHz Input Gain 1dB step Volume Control 1dB step Treble Control 2dB step Bass Control 2dB step Middle Control 2dB step Fader and Balance Control 1dB step Loudness Control 1dB step Mute Attenuation 0 -63 -14 -14 -14 -79 0 100 Min. 6 2.1 Typ. 9 2.6 0.01 111 95 15 16 +14 +14 +14 0 20 0.8 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB dB dB dB
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BLOCK DIAGRAM
2.2F 47nF IN_L
MUXOUT_L 21 20 12 44 30 31 25 24
LOUD_L
TREBL_L
5.6nF
2.7K 22nF 100nF
5.6K 18nF 100nF
MID_LO
MID_LI
BASS_LO
BASS_LI
4 x 470nF
STEREO1_L
16
STEREO2_L SPKR ATT
17 34 OUT_LF
STEREO3_L
18
STEREO4_L INGAIN TREBLE MIDDLE S-MUTE VOLUME + LOUDN BASS
15
2 x 4.7F
DIFF_L
14
SPKR ATT
33
OUT_LR
DIFFGND_L I2C BUS DECODER + LATCHES
13
40 38 37 36
ADDR SCL SDA DIGGND
STEREO1_R
8
STEREO2_R
9
STEREO3_R INGAIN MIDDLE VOLUME + LOUDN TREBLE BASS
10 S-MUTE SPKR ATT 29 OUT_RR
STEREO4_R
7
2 x 4.7F
DIFF_R
6
DIFFGND_R
5 MUTE CONTROL SOFT, ZERO SPKR ATT 32 OUT_RF
DVDD
41
AVDD 39 CREF IN_R TREB_R 22F 47nF 2.2F LOUD_R 3 2 4 1
42 23 MID_RO 5.6nF
SUPPLY 22 MID_RI 27 BASS_RI 26 SMEXT 28 35 PAUSE 19 CSM
D95AU249B
43
AGND
MULTIPLEXER
5 x 470nF
MONO
11
MUXOUT_R
22nF 2.7K
18nF 100nF 5.6K
BASS_RO)
100nF
47nF
47nF
TDA7437N
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ELECTRICAL CHARACTERISTICS (AVDD, DVDD = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol RI VCL SI RL GI MIN GI MAX Gstep Ea VDC Parameter Input Resistance Clipping Level Input Separation Output Load Resistance Minimum Input Gain Maximum Input Gain Step Resolution Set Error DC Steps Adiacent Gain Steps GIMIN to GIMAX DIFFERENTIAL INPUT (Pin 5, 6, 13, 14) RI CMRR d eIN GDIFF Input Resistance Common Mode Rejection Ratio Distortion Input Noise Differential Gain Input selector BIT D4 = 0 (0dB) Input selector BIT D4 = 1(-6dB) VCM = 1VRMS ; f = 1KHz VI = 1VRMS 20Hz to 20KHz; Flat; D6 = 0 D4 = 0 D4 = 1 VOLUME CONTROL RI GMAX AMAX ASTEPC EA Et VDC Input Resistance Maximum Gain Maximum Attenuation Step Resolution Coarse Atten. Attenuation Set Error Tracking Error DC Steps Adjacent Gain Steps Adjacent Attenuation Steps From 0dB to AMAX LOUDNESS CONTROL (Pin 4, 12) RI AMAX Astep VTH Internal Resistor Maximum Attenuation Step Resolution Zero Crossing Threshold(note 1) WIN = 11 WIN = 10 WIN = 01 WIN = 00 AMUTE Mute Attenuation 80 Loud = On 35 19 0.5 50 20 1 35 70 140 280 100 65 21 1.5 K dB dB mV mV mV mV dB -5 -3 0.5 G = 16 to -20dB G = -20 to -63dB Pin 2 and 20 31 15 61 0.5 -1.0 -2.75 44 16 63.75 1.0 0 57 17 66.5 1.5 1.0 2.75 2 +5 +3 5 K dB dB dB dB dB dB mV mV mV -1 -7 10 14 45 15 20 70 0.01 5 0 -6 1 -5 0.08 20 26 K K dB % V dB dB Test Condition pin 7 to 11 and 15 to 18 d 0.3% Min. 70 2.1 80 2 -0.75 14 0.5 -1.0 0 15 1.0 0 0.5 3 +0.75 16 1.5 1.0 10 Typ. 100 2.6 95 Max. 130 Unit K VRMS dB K dB dB dB dB mV mV INPUT SELECTOR (MONO AND STEREO INPUTS)
ZERO CROSSING MUTE
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ELECTRICAL CHARACTERISTICS (continued) (AVDD, DVDD = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol VDC AMUTE TDON TDOFF RINT VSMH VSML Crange Astep Rg Crange Astep Rg CRANGE Astep CRANGE Astep AMUTE EA VDC Vclip RL RO VDC VTH DC Step Mute Attenuation ON Delay Time OFF Current Pullup Resistor (pin 28) (pin 28) Level High (pin 28) Level Low Control Range Step Resolution Internal Feedback Resistance Control Range Step Resolution Internal Feedback Resistance Control Range Step Resolution Control Range Step Resolution Output Mute Attenuation Attenuation Set Error DC Steps Clipping Level Output Load Resistance Output Impedance DC Voltage Level Pause Threshold WIN = 11 WIN = 10 WIN = 01 WIN = 00 IDELAY VTHP Pull-Up Current Pause Threshold 15 AV = 0 to -40dB Data Word = 1111XXXX AV = 0 to -40dB Adjacent Attenuation Steps d = 0.3% 2.1 2 50 3.5 90 3.8 35 70 140 280 25 3.0 35 140 4.1 0.1 2.6 0.5 80 Soft Mute Active 11.5 1 31 11.5 1 17.5 13 1 14 2 44 14 2 25 14 2 79 1 100 1.5 3 1.5 CCSM = 22nF; 0 to -20dB; I = IMAX CCSM = 22nF; 0 to -20dB; I = IMIN VCSM = 0V; I = IMAX VCSM = 0V; I = IMIN (note 2) 3.5 1 16 3 57 16 3 32.5 15 3 SOFT MUTE 50 0.8 25 20 65 1.5 45 40 2 100 2.0 60 60 dB ms ms mA A K V V dB dB K dB dB K dB dB dB dB dB dB mV Vrms K V mV mV mV mV A V Parameter Test Condition 0dB to Mute Min. Typ. 0.1 Max. 3 Unit mV
BASS CONTROL
MIDDLE CONTROL
TREBLE CONTROL
SPEAKER ATTENUATORS
AUDIO OUTPUT
PAUSE DETECTOR
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ELECTRICAL CHARACTERISTICS (continued) (AVDD, DVDD = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol GENERAL VCC ICC PSRR eNO Et S/N SC d VIL VlN IlN VO Supply Voltage Supply Current Power Supply Rejection Ratio Output Noise Total Tracking Error Signal to Noise Ratio Channel Separation L - R Distortion Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO = 1.6mA 3 -5 0.1 5 0.4 VIN =1V all gain = 0dB f = 1KHz Output Muted (B = 20 to 20kHz flat) All Gains 0dB(B = 200 to 20kHz flat) AV = 0 to -20dB AV = -20 to -60dB All Gains = 0dB; VO = 2.1Vrms 80 6 7 70 9 10 90 4 6 0 0 111 95 0.01 0.08 1 15 1 2 10.2 13 V mA dB V V dB dB dB dB % V V A V Parameter Test Condition Min. Typ. Max. Unit
BUS INPUTS
Note 1: WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold Note 2: Internall pullup resistor to Vs/2; "LOW" = softmute active Note: The ANGND and DIGGND layout wires must be kept separated. A 50 resistor is recommended to be put as far as possible from the device.
The CLD - and CDR - can be shortcircuited in applications providing 3 wires CD signal
L+ L- =RR+
L+
CD
LRR+
TDA7437N
D02AU1384
CLD - = DIFFINLGND CDR - = DIFFINRGND
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I2C BUS INTERFACE Data transmission from microprocessor to the TDA7437N and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.A STOP conditions must be sent before each START condition. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 3). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse.The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data.This approach of course is less protected from misworking and decreases the noise immunity. Figure 1. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 2. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 3. Acknowledge on the I2CBUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
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SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises:
s s s s s
A start condition (s) A chip address byte,(the LSB bit determines read (=1)/write (=0) transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
CHIP ADDRESS MSB LSB 0 0 1 MSB I SUBADDRESS LSB A3 A2 A1 A0 ACK DATA 1 to DATA n MSB DATA LSB ACK P
S1
0
0 A R/W ACK X X X
ACK = Acknowledge; S = Start; P = Stop; I = Auto Increment; X = Not used MAX CLOCK SPEED 500kbits/s ADDRpin open A=0 ADDRpin close to Vs A = 1 AUTO INCREMENT If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled SUBADDRESS (receive mode)
MSB X X X I A3 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 LSB A0 0 1 0 1 0 1 0 1 0 1 Input Selector Loudness Volume Bass, Treble Speaker Attenuator LF Speaker Attenuator LR Speaker Attenuator RF Speaker Attenuator RR Input Gain Middle Mute FUNCTION
TRANSMITTED DATA Send Mode
MSB X X X X X SM ZM LSB P
P = Pause (Active low) ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used
The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chipaddress.
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DATA BYTE SPECIFICATION
MSB D7 D6 D5 D4 D3 1 1 1 1 1 1 X X X 0 0 1 1 X 0 1 0 1 0 D2 0 0 0 0 1 1 X D1 0 0 1 1 0 0 X LSB D0 0 1 0 1 0 1 X FUNCTION DIFFERENTIAL STEREO 1 STEREO 2 STEREO 3 STEREO 4 MONO DC CONNECT (1) HALF-DIFF 0dB (*) HALF-DIFF -6dB (*) FULL-DIFF 0dB (**) FULL-DIFF -6dB (**)
(*) Selected when using a 3 wires differential source (pins 5 and 13 shorted) (**) Selected when using 4 wires differential source (1) OUTR-INR (OUTL-INR) short circuited internally (no need external connection)
Loudness
MSB D7 D6 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 FUNCTION LOUDNESS STEP 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 15dB 16dB 17dB 18dB 19dB 20dB LOUDNESS OFF FINE VOLUME 0dB -0.25dB -0.5dB -0.75dB
0 0 1 1
0 1 0 1
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Mute
MSB D7 D6 D5 D4 D3 0 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 D2 D1 LSB D0 1 1 1 FUNCTION Soft Mute On Soft Mute with fast slope Soft Mute with slow slope Zero Mute Direct Mute Reset Zerocross window (280mV) Zerocross window (140mV) Zerocross window (70mV) Zerocross window (35mV) Nonsymmetrical Bass Symmetrical Bass
Volume
MSB D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 X 0 0 0 0 1 1 1 1 0 0 X 0 0 1 1 0 0 1 1 0 0 X 0 1 0 1 0 1 0 1 0 1 X X X X 16dB 8dB 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB MUTE D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB FUNCTION
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Speaker
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 X X X D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 FUNCTION 1.25dB step 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB MUTE
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Bass Treble
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 FUNCTION TREBLE STEP -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB BASS STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 126B 14dB
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Input Stage Gain Middle
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION IN-GAIN STEP 0dB 1dB 2dB 3dB 4dB 5dB 6dB 7dB 8dB 9dB 10dB 11dB 12dB 13dB 14dB 15dB MIDDLE STEP -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 126B 14dB
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MUTE & PAUSE FEATURES The TDA7437N provides three types of mute, controlled via I2C bus (see pag. 10, MUTE BYTE register). SOFT MUTE Bit D0 = 1 Soft Mute ON Bit D0 = 0 Soft Mute OFF It allows an automatic soft muting and unmuting of the signal. The time constant is fixed by an external capacitor Csm inserted between pin Csm and ground. Once fixed the external capacitor, two different slopes (time constant) are selectable by programmation of bit D1. Bit D1 = 0 fast slope (I=Imax) Bit D1 = 1 slow slope (I=Imin) The soft mute generates a gradual signal decreasing avoiding big click noise of an immediate high attenuation, without necessity to program a sequence of decreasing volume levels. A response example is reported in Fig.8 (mute) and Fig.9 (unmute). The final attenuation obtained with soft mute ON is 60dB typical. The used reference parameter is the delay time taken to reach 20dB attenuation (no matter what the signal level is). Using a capacitor Csm = 22nF this delay is: d = 1. 8mswhen selected Fast slope mode (bit D1=0) d = 25 ms when selected Slow slope mode (bit D1=1 In application, the soft mute ON programmation should be followed by programmation of DIRECT MUTE ON (see later) in order to achieve a final 100dB attenuation.Beside the I2C bus programmation, the Soft Mute ON can be generated in a fast way by forcing a LOW level at pin SMEXT (TTL Level compatible). This approach is recommended for fast RDS AF switching. The Soft Mute status can be detected via I2C bus, reading the Transmitted Byte, bit SM (see data sheet pag. 8). read bit SM = 1 soft mute status ON read bit SM = 0 soft mute status OFF DIRECT MUTE bit D3 = 1 Direct mute ON bit D3 = 0 Direct nute OFF The direct mute bit forces an internal immediate signal connection to ground. It is located just before the Volume/Loudness stage, and gives a typical 100dB attenuation. SPEAKERS MUTE An additional direct mute function is included in the speakers attenuators stage. The four output LF, RF, LR, RR can be separately muted by setting the speaker attenuator byte to the value 01111111 binary. Typical attenuation level 100dB. This mute is useful for fader and balance functions. It should not be applied for system mute/unmute, because it can generate noise due to the offset of previous stages (bass /treble). ZEROCROSSING MUTE bit D2 = 1 D4 = 0 zero crossing mute ON bit D2 = 0 D4 = 0 zero crossing mute OFF The mute activation/deactivation is delayed until the signal waveform crosses the DC zero level (Vref level).
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The detection works separately for the left and the right channels (see Figg. 10, 11). Four different windows threshold are software selectable by two dedicated bits. bit D6 bit D5 WINDOW 0 0 1 1 0 1 0 1 Vref DC +/-280mV Vref DC +/-140mV Vref DC +/-70mV Vref DC +/-35mV
The zero crossing mute activation/deactivation starts when the AC signal level falls inside the selected window (internal comparator). The ZEROCROSS Mute (and Pause) detector is always active. It can be disabled, if the feature is not used, by forcing the bit D4 = 1 Zero crossing and Pause detector reset. In this way the internal comparator logic is stopped, eliminating its switching noise. The zero cross mute status is detected reading the Transmitted Byte bit ZM. bit ZM = 1 zero cross mute status ON bit ZM = 0 zero cross mute status OFF PAUSE FUNCTION On chip is implemented a pause detector block. It uses the same 4 windows threshold selectable for the zero crossing mute, bit D6,D5 byte MUTE (see above). The detector can be put in OFF by forcing bit D4 = 1, otherwise it is active. The Pause detector info is available at PAUSE pin. A capacitor must be connected between PAUSE pin and Ground. When the incoming signal is detected to be outside the selected window, the external capacitor is discharged. When the signal is inside the window, the capacitor is integrating up (see Figg.12 and 13). a by reading directly the Pause pin level.The ON/OFF voltage threshold is 3.0V typical.Pause OFF = level low (< 3.0V)Pause ON = level high ( ; 3.0V) b by reading via I2C bus the Transmitted Byte, bit PP = 0 pause active.P = 1 no pause detected. The external capacitor value fixes the time constant. The pull up current is 25uV typicalWith input signal Vin = 1Vrm --; Vdc pin pause = 15mV Vin = 0Vrms --; Vdc pin pause = 5.62V For example choosing Cpause = 100nF the charge up constant is about 22ms. Instead with Cpause = 15nF the charge up constant is about 360s. The Pause detection is useful in applications like RDS, to perform noiseless tuning frequeny jumps avoiding to mute the signal. NO SYMMETRICAL BASS CUT RESPONSE bit D7 = 0 No symmetrical bit D7 = 1 Symmetrical The Bass stage has the option to generate an unsymmetrical response, for cut mode settings (bass level from -2db to - 14dB) For example using a T-type band pass externa The feature is useful for human ear equalization in noisy enviroments like cars etc. See examples in Fig. 14 (symmetrical response) and Fig. 15 (unsymmetrical response).
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TRANSMITTED DATA (SEND MODE) bit bit bit bit bit bit bit bit P=0 P=1 Pause active No pause detected
ZM = 1 Zero cross mute ON ZM = 0 Zero cross mute OFF SM = 1 Soft mute ON SM = 0 Soft mute OFF ST = 1 Stereo signal detected (input MPX) ST = 0 Mono signal detected (input MPX)
The TDA7437N allows the reading of four info bits. The type (Stereo/Mono) of received broadcasting signal is easily checked and displayed by using the ST bit. The P bit check is useful in tuning jumps without signal muting. The SM soft mute status becomes active immediately, when bit D0 is set to 1 (soft mute ON, MUTE byte) and not when the signal level has reached the 60 dB final attenuation. TDA7437N I2C BUS PROTOCOL The protocol is standard I2C, using subaddress byte plus data bytes (see pagg. 8 to 13). The optional Autoincrement mode allows to refresh all the bytes registers with transmission of a single subaddress, reducing drastically the total transmission time. Without autoincrement, subaddress bit I = 0, to refresh all the bytes registers (10), it is necessary to transmit 10 times the chip address, the subaddress and the data byte. Working with a 100Kb/s clock speed the total time would be : [(9*3+2)*10]bits*10us=2.9ms Instead using autoincrement mode, subaddress bit I=1, the total time will be: (9*12+2)*10us=1.1ms. The autoincrement mode is useful also to refresh partially the data. For example to refresh the 4 speakers attenuators it is possible to program the subaddress Spkr LF (code XX010100), followed by the data byte of SPKR LF, LR, RF, RR in sequence. Note:that the autoincrement mode has a module 16 counter, whereas the total used register bytes are 10. It is not correct to refresh all the 10 bytes starting from a subaddress different than XX010000. For example using subaddress XX010010 (volume) the registers from Volume to Mute (see pag. 8) are correctly updated but the next two transmitted bytes instead to refer to the wanted Input selector and Loudness are discharged. (the solution in this case is to send two separated pattern in autoinc mode, the first composed by address, subaddress XX010010, 8 data bytes, and the second composed by address, subaddress XX010000, 2 data bytes). With autoincrement disabled, the protocol allows the transmission in sequence of N data bytes of a specific register, without necessity to resend each time the address and subaddress bytes. This feature can be implemented, for example, if a gradual Volume change has to be performed (the MCU has not to send the STOP condition, keeping active the TDA7437N communication) WARNING The TDA7437N always needs to receive a STOP condition, before beginning a new START condition. The de16/23
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vice doesn't recognize a START condition if a previously active communication was not ended by a STOP condition. I2C BUS READ MODE The TDA7437N gives to the master a 1 byte "TRANSMITTED INFO" via I2C bus in read mode. The read mode is Master activated by sending the chip address with LSB set to 1, followed by acknowledge bit. The TDA7437N recognizes the request. At the following master generated clocks bits, the TDA7437N issues the TRANSMITTED INFO byte on the SDA data bus line (MSB transmitted first). At the nineth clock bit the MCU master can: - acknowledge the reception, starting in this way the transmission of another byte from the TDA7437N. - no acknowledge, stopping the read mode communication. LOUDNESS STAGE The previous SGS-THOMSON audioprocessors were implementing a fixed loudness response, only ON/OFF sw programmable. No possibility to change the loud boost rate at a certain volume level. The TDA7437N implements a fully programmable loudness control in 20 steps of 1dB. It allows a customized loudness response for each application. The external network connected to the loudness pins LOUD_L and LOUD_R fixes the type of loudness response 1)Simple CapacitorThe loudness effect is only a boost of low frequencies. (see Fig. 16) 2)Second order Loudness (boost of low and high frequencies). 3)Second order decreased type Loudness (lower boost of low and high frequencies). 4)Second order modified type Loudness (higher boost of low and high frequencies). BASS & MID FILTERS Several bass filter types can be implemented. Normally it is used the basic T-type Bandpass Filter.Starting from the filter component values (R1 internal and R2, C1, C2 external), the centre frequency Fc, the gain Av at max bass boost and the filter Q factor are computed as follows 1 F c = -----------------------------------------------------------------2 R1 R 2 C1 C2 R2 C2 + R2 C 1 + R1 C1 A v = -------------------------------------------------------------------------R 2 C1 + R2 C 2 ( R 1 R2 C1 C 2 ) Q = -----------------------------------------------------R2 C1 + R2 C 2 Viceversa fixed Fc, Av, and R1 (internal typ.30%), the external component values are Av - 1 C1 = --------------------------------2 R1 Q Q Q C1 C2 = ----------------------------------Av - 1 - Q Q
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TDA7437N
Av - 1 - Q Q R2 = --------------------------------------------------------------------2 C1 F c ( A v - 1 ) Q TREBLE STAGE The Treble stage is a simple high pass filter which time constant is fixed by internal resistor (50Kohm typ) and an external capacitor connected between pins TREB_R/TREB_L and Ground. IN-OUT PINS The multiplexer output is available at OUT_R and OUT_L pins for optional connection of external graphic equalizer (TDA7316/TDA7317), surround chip (TDA7346) etc. The signal is fed in again at pins IN_L and IN-R. In case of application without external devices the pins OUT_L/OUT_R and IN_L/IN_R can be left unconnected if bit D3 byte input selector is forced = 0 (DC connect) instead if bit D3 is kept = 1 an external decoupling capacitor must be provided between OUTR/INR and OUTL/INR necessary to avoid signal DC jumps, generating "Clicking" output noise.The input impedance of the next volume stage is 44Kohm typical (minimum 31Kohm). A capacitor no lower than 1mF should be used. INPUT SELECTOR The multiplexer selector can choose one of the following inputs: - a differential CD stereo input. - a mono input. - four stereo input The signal fed to the input pins must be decoupled via series capacitors. The minimum allowed value depends on the correspondent input impeance. For the CD diff input (Zi = 10Kohm worst case ) a Cin = 4.7uF is recommended. For the other inputs (70Kohm worst case,a Cin=1uF is recommended.
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TDA7437N
Figure 4. Power on Time Constant vs CREF Capacitor CREF = 4.7F
V (1V/div)
D95AU380
Figure 7. SVRR vs. Frequency
SVRR (dB) -40 -50
F 22
D95AU383
4.7F
-60
10 F
47F
-70 -80
OUT LF CREF 2 1
-90 -100 10 100 1K
VS=8V Ripple=0.2VRMS AV=-15dB
10K
Freq(Hz)
BWL
0.5s/DIV TIME
Figure 5. Power on Time Constant vs CREF Capacitor CREF = 10F
V (1V/div)
D95AU381
Figure 8. Soft Mute ON
SOFT MUTE=ON SLOPE=FAST Vout=500mVrms V
D95AU384
Main Menu
Pin Csm
V
OUT LF CREF
2 1
BWL
0.5s/DIV
TIME
Vout
Chan 2 1ms 0.2V Chan 3 1ms 2V
Figure 6. Power on Time Constant vs CREF Capacitor CREF = 22F
V (1V)
D95AU382
SOFT MUTE
CH1 9V DC
x CH1 0.5V 10 ~ TIME x CH2 20mV10 ~ x CH3 0.2V10 = x CH4 20mV 10 = T/div 1ms
OUT LF CREF
2 1
BWL
1s/DIV
TIME
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TDA7437N
Figure 9. Soft Mute OFF
SOFT MUTE=OFF SLOPE=FAST Vout=500mVrms V
D95AU387
Figure 12. Pause Detector
PAUSE DETECTOR ZCW=140mV Cpause=100nF D02AU1385 V Vout Main Menu
Main Menu
Pin Csm
Chan 1 20ms 0.2V
V
Chan 2 20ms 2V CH2 4.12V DC
Vout Chan 2 1ms 0.2V Chan 1 1ms 2V
TIME
Figure 13. Pause Detector
PAUSE DETECTOR ZCW=140mV Cpause=100nF
D02AU1386
CH1 9V DC SOFT MUTE
TIME
Vout
Figure 10. Zero Crossing Mute ON
ZERO CROSSING MUTE = ON V Panel STATUS Memory Save PANEL Recall Auxiliary Setups Memory Card X-Y mode Persistance mode Return RIGHT CH2 528mV DC TIME LEFT
D95AU389
Main Menu
x Chan 1 0.5ms 0.2V x Chan 2 0.5ms 0.2V
Chan 2 20ms 2V Chan 3 20ms 0.2V CH2 4.08V DC
x CH1 20mV10 ~ x BWL CH2 0.2V 10x= CH3 20mV 10 ~ x CH4 5mV 10 ~ T/div 20ms
Figure 11. Zero Crossing Mute OFF
ZERO CROSSING MUTE = OFF V Main Menu LEFT
D95AU390
Figure 14. Sym _Bass
(dB)
D95AU393
RIGHT
x Chan 2 0.2ms 1V x Chan 1 0.2ms 0.5V
10 5 0 -5 -10 -15 10 100 1K 10K Freq(Hz)
Multi Zoom off
2ms
CH1 2.7V DC
TIME
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TDA7437N
Figure 15. Non_Sym _Bass
ATT (dB) 10 5 0 -5 -10 -15 -20 -25 10 100 1K 10K Freq(Hz)
D95AU394
Figure 16. Loudness
ATT (dB) 18 16 14 12 10 8 6 4 2 0 10 100 1K 10K Freq(Hz)
D98AU887
Figure 17. Test Board Diagram
GND VCC CON1
C17 22F
C18 100nF JP2 JP1 C19 5.6nF TRL
R4 2.7K
R3 5.6K
C11 18nF
C10 22nF
C8 100nF
C7 100nF
C16 22F
AGND
DVDD
ADDR
AVDD
MIDRI 31
MIDRO 30
BASSRO 27
BASSRI 26 39
CREF 25 BASSLO
C20 5.6nF
C6 100nF
TRR IN_R
44 1 2
43
42
41
40
C21 2.2F C22 4.7nF CON4 C23 4.7F DIFG_R C24 4.7F DIFF_R C25 470nF ST4_R C26 470nF ST1_R C27 470nF ST2_R C28 470nF ST3_R C29 470nF MONO C30 4.7nF LOUDR DIFG_R O_R
24
BASSLI
C5 100nF
3
23
MIDLO
C4 22nF
R2 5.6K
LOUDR
4
22 20
MIDLI I_L
C3 18nF
5 21 6 38 28 37 36 9 O_L SCL SMEX SDA DGND
C2 2.2F
R1 2.7K
CON2 SCL JP3 SMEX SDA DGND R5 50 C14 CON3 LF C13 RF C12 LR C9 RR GND
DIFF_R
ST4_R
7
ST1_R
8
ST2_R
ST3_R
10 34 11 33 12 13 DIFF_R 14 ST4_R 15 ST1_R 16 ST2_R 17 ST3_R 18 CSM 19 PAUSE 35 29 OUTLF
MONO
RF
CON5
32
LR
DIFG_R DIFG_L C31 4.7F DIFF_L C32 4.7F ST4_L C33 470nF ST1_L C34 470nF ST2_L C35 470nF ST3_L C36 470nF
OUTRR
C1 2.2nF
C15 10F
D98AU882
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TDA7437N
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B
C
e
L
K
TQFP4410
0076922 D
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TDA7437N
Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
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